Historically, Design Compiler used Wire Load Models (WLM) to estimate interconnect delays. In modern sub-micron designs, wire resistance and capacitance dominate total delay.
Converting the RTL description into an intermediate, technology-independent format (GTECH library blocks).
The P&R tool (like ICC2 or Innovus) needs to know the timing constraints you defined.
############################################################################### # Synopsys Design Compiler Automation Script (2021 Reference Flow) ############################################################################### # Step 1: Initialize Setup and Libraries source ../scripts/.synopsys_dc.setup # Step 2: Analyze and Elaborate Design set RTL_FILES [list ../rtl/top_module.v ../rtl/sub_module1.v] analyze -format data_files $RTL_FILES elaborate top_module current_design top_module # Ensure the design structural integrity link check_design > ../reports/initial_check.rpt # Step 3: Apply Constraints source ../scripts/constraints.tcl # Step 4: Synthesize Design compile_ultra # Step 5: Generate Output Reports report_design > ../reports/design_summary.rpt report_area -hierarchy > ../reports/area_final.rpt report_timing -max_paths 20 > ../reports/timing_final.rpt report_power > ../reports/power_final.rpt # Step 6: Export Deliverables change_names -rules verilog -hierarchy write -format verilog -hierarchy -output ../mapped/top_module_mapped.v write_sdc ../mapped/top_module_final.sdc write -format ddc -hierarchy -output ../mapped/top_module_final.ddc echo "Design Compiler Synthesis Optimization Completed Successfully!" exit Use code with caution. synopsys design compiler tutorial 2021
# -hierarchy keeps the hierarchy if not ungrouped write -format verilog -hierarchy -output netlist/my_design_netlist.v
For complex designs, compile_ultra is the industry standard. It enables advanced optimization algorithms, including:
This public link is valid for 7 days and shares a thread, including any personal information you added. This link or copies made by others cannot be deleted. If you share with third parties, their policies apply. Can’t copy the link right now. Try again later. Historically, Design Compiler used Wire Load Models (WLM)
# Define clock uncertainty (jitter and margin) set_clock_uncertainty 0.2 [get_clocks clk]
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analyze -format verilog -lib WORK top_module.v alu.v elaborate top_module -lib WORK The P&R tool (like ICC2 or Innovus) needs
set my_design "riscv_core"
: If the tool outputs errors stating components cannot be linked, double check your .synopsys_dc.setup paths. Ensure that all standard cell packages ( .db ) and design block files are present in the search list.
The tool must parse the RTL files and verify syntax correctness before optimization.
